library verilog;
use verilog.vl_types.all;
entity DPR16X2B is
    port(
        DI0             : in     vl_logic;
        DI1             : in     vl_logic;
        WAD0            : in     vl_logic;
        WAD1            : in     vl_logic;
        WAD2            : in     vl_logic;
        WAD3            : in     vl_logic;
        WRE             : in     vl_logic;
        WCK             : in     vl_logic;
        RAD0            : in     vl_logic;
        RAD1            : in     vl_logic;
        RAD2            : in     vl_logic;
        RAD3            : in     vl_logic;
        WDO0            : out    vl_logic;
        WDO1            : out    vl_logic;
        RDO0            : out    vl_logic;
        RDO1            : out    vl_logic
    );
end DPR16X2B;
